Dyber designs and manufactures post-quantum cryptographic hardware. From PCIe accelerators and chiplets to embedded secure elements and cloud infrastructure, we deliver quantum-safe security across every layer of your stack.
Hardware accelerators, silicon IP, embedded security, software, and cloud. Every layer purpose-built for post-quantum cryptography.
QUAC-100 Rev B1
PCIe-based cryptographic accelerator purpose-built for post-quantum cryptography. 16 parallel Radix-32 NTT engines, integrated QRNG, sub-microsecond latency.
TCG-compliant TPM 2.0 enhanced with NIST post-quantum algorithms. TSSOP-28 package, LPC/SPI bus, hybrid ML-DSA-65 and ML-KEM-768 modes.
Dedicated PQC accelerator chiplet for SoC integration. Proprietary QLI (Quantum Lattice Interface) bus.
Post-quantum secure element in a 5x5mm QFN-20 package. ML-KEM-512, ML-DSA-44 hardware acceleration. Under 10mW active power.
Hardware quantum random number generator. USB, PCIe, and network form factors. Up to 1 Gbps entropy output. SP 800-90B compliant.
Architecture-agnostic PQC IP cores for SoC integration. AXI4, APB, AHB standard interfaces. FPGA-validated, x86/ARM/RISC-V support.
Network-attached Hardware Security Module with native PQC. 1U rackmount, PKCS#11 interface, integrated QRNG, enterprise key management.
Full PQC acceleration in an M.2 2242 form factor. PCIe 3.0 x1, integrated QRNG, 50K+ operations per second at just 5 watts.
8 language bindings. Linux and Windows. Apache 2.0 license.
Type 1 hypervisor with integrated PQC. KVM-based, bare-metal.
PQC as a service. Hardware-accelerated via REST. <50ms global.
Cloud-native EDA for cryptographic hardware verification.
| ML-KEM-512 | CPU (i7 AVX2) | QUAC-100 | Speedup |
|---|---|---|---|
| KeyGen | ~8.7 µs | 180 ns | ~48x |
| Encapsulation | ~10.8 µs | 220 ns | ~49x |
| Decapsulation | ~13.4 µs | 280 ns | ~48x |
| Full Cycle | ~32.9 µs | ≤700 ns | ~47x |
FIPS 203 ML-KEM-512. CPU baseline: Intel Core i7-13700K with AVX2. QUAC-100 Rev B1 silicon, PCIe Gen5 x8x8.
Dyber is a Delaware C-Corporation founded in 2024, headquartered in Annapolis, Maryland, minutes from Washington D.C. and major federal agencies. We build hardware-accelerated post-quantum cryptography solutions for government, financial services, critical infrastructure, healthcare, and defense contractors.
CNSA 2.0 compliant. ITAR compatible. Built for classified and sensitive workloads.
Sub-microsecond crypto for HFT, payment processing, and secure inter-bank communication.
Drop-in PQC for TLS termination, key management, and encrypted storage at scale.
First PQC-native TPM and Secure Element for IoT. QuantaSE: 5x5mm, under 10mW.
Synthesizable PQC IP cores for your own silicon. x86, ARM, RISC-V targets.
from dyber import kem
# Auto-detects QUAC-100 hardware
pk, sk = kem.keygen("ML-KEM-768")
ct, ss = kem.encapsulate(pk)
ss2 = kem.decapsulate(sk, ct)
assert ss == ss2 # quantum-safe shared secretpip, cargo, apt, or brew. 8 language bindings. Apache 2.0 license.
OpenSSL provider, BoringSSL provider, or direct API. QUAC-100 auto-detected.
keygen, sign, encapsulate, decapsulate. ML-KEM, ML-DSA, SLH-DSA. One interface.
Hardware-accelerated when QUAC-100 is present. Software fallback when it's not. Zero code changes.
Pilot program now accepting applications. Request evaluation hardware or talk to our engineering team.