Downloads
Downloadable resources for the Dyber PQC Silicon IP portfolio. Public documentation is freely accessible. Evaluation packages, RTL deliverables, and detailed datasheets require a signed evaluation agreement.
Datasheets #
Summary datasheets are available publicly. Detailed datasheets with measured FPGA resource utilization and performance figures require NDA.
| Document | Description | Access |
|---|---|---|
| PQC IP Portfolio Overview | Two-page summary of the complete IP portfolio, core descriptions, and target applications | Public |
| NTT Engine Family Datasheet | Architecture overview, configuration options, and relative performance comparison for NTT-R2 through NTT-R16 | Public |
| DYBER-MLKEM Datasheet | ML-KEM accelerator architecture, operation descriptions, interface summary, and integration overview | Public |
| DYBER-MLDSA Datasheet | ML-DSA accelerator architecture, rejection sampling pipeline, verify-only configuration | Public |
| DYBER-SLH Datasheet | SLH-DSA hash-based signature accelerator overview and parameter sets | Public |
| Detailed Performance Report | FPGA-measured resource utilization (LUTs, DSPs, BRAM), exact latencies, throughput, and power figures for all cores | NDA Required |
| ASIC Estimation Guide | Gate count estimates, expected frequency/power at target process nodes, area projections | NDA Required |
Evaluation Packages #
90-day evaluation packages include encrypted RTL (simulation only — no synthesis rights), the complete UVM verification environment, NIST KAT test vectors, and reference simulation scripts. Evaluation licenses are free of charge.
| Package | Contents | Access |
|---|---|---|
| EVAL-MLKEM | DYBER-MLKEM (all security levels) + NTT-R4 + SHA3/SHAKE + UVM testbench | Eval Agreement |
| EVAL-MLDSA | DYBER-MLDSA (all security levels) + NTT-R4 + SHA3/SHAKE + UVM testbench | Eval Agreement |
| EVAL-SLH | DYBER-SLH (128f, 128s, 256f) + KECCAK-CORE + UVM testbench | Eval Agreement |
| EVAL-NTT | NTT-R2/R4/R8/R16/R32 standalone + MOD-BARRETT + MOD-MONT + UVM testbench | Eval Agreement |
| EVAL-FULL | Complete portfolio evaluation — all algorithm accelerators, all primitives, full UVM suite | Eval Agreement |
Evaluation packages include encrypted RTL suitable for simulation with Synopsys VCS, Cadence Xcelium, Siemens Questa, or Verilator. Synthesis and physical implementation require a development or production license. Request an evaluation at ip-sales@dyber.com.
Reference Designs #
| Design | Platform | Description | Access |
|---|---|---|---|
| PQC Accelerator on Zynq | Zynq UltraScale+ ZCU106 | Complete block design with ARM PS host, AXI interconnect, DYBER-MLKEM + DYBER-MLDSA. Includes Linux driver and user-space demo application. | Dev License |
| NTT Benchmark Suite | Any Xilinx UltraScale+ | Standalone NTT-R2/R4/R8/R16 benchmark with performance measurement infrastructure and automated throughput reporting. | Eval Agreement |
| TLS Offload Proof-of-Concept | Alveo U250 / U280 | DYBER-TLS engine integrated with 100G Ethernet subsystem. Demonstrates PQC TLS handshake offload at line rate. | Dev License |
| IoT Security Element | Zynq-7000 (ZC706) | Minimal NTT-R2 + ML-KEM-512 configuration demonstrating PQC in constrained environments. MicroBlaze soft-processor host. | Eval Agreement |
Driver & Software #
| Package | Description | Access |
|---|---|---|
| Bare-Metal Driver Library | C/C++ register-level driver library. Architecture-independent. Supports all Dyber IP cores with unified API. Includes HAL templates for Linux, FreeRTOS, and bare-metal. | Eval Agreement |
| Linux Kernel Module | Reference character device driver for /dev/dyber_pqc. x86-64 and ARM64. DMA support, interrupt handling, sysfs status interface. | Dev License |
| User-Space Demo | Command-line tool demonstrating all PQC operations (keygen, encaps, decaps, sign, verify) via the Linux driver interface. | Eval Agreement |
| OpenSSL Engine | OpenSSL 3.x provider that routes PQC operations to Dyber hardware. Drop-in acceleration for existing OpenSSL-based applications. | Dev License |
| API Documentation | Doxygen-generated C API reference covering all driver functions, parameters, return codes, and usage examples. | Public |
Documentation #
| Document | Description | Access |
|---|---|---|
| Integration Guide | SoC integration methodology, AMBA interface details, FPGA and ASIC integration paths | Public (this site) |
| Register Map Reference | Complete register definitions for all IP cores with bit-field descriptions | Public (this site) |
| Security Architecture | Constant-time design, masking, fault detection, key isolation | Public (this site) |
| FIPS Boundary Documentation | Security policy, boundary definition, self-test specification for FIPS 140-3 submission | NDA Required |
| Common Criteria Security Target | ST document for EAL4+ evaluation | NDA Required |
| TVLA Evaluation Report | Side-channel leakage assessment methodology and results for masked variants | NDA Required |
NIST Test Vectors #
NIST Known Answer Test (KAT) vectors for algorithm validation are freely available from NIST. Dyber's verification suite includes pre-formatted versions optimized for hardware simulation.
| Vector Set | Source | Format |
|---|---|---|
| ML-KEM (FIPS 203) | NIST CAVP | UVM stimulus files + raw JSON |
| ML-DSA (FIPS 204) | NIST CAVP | UVM stimulus files + raw JSON |
| SLH-DSA (FIPS 205) | NIST CAVP | UVM stimulus files + raw JSON |
| SHA-3 / SHAKE | NIST CAVP | Standard CAVP format + UVM sequences |
| ACVP Vector Sets | NIST ACVTS | JSON format compatible with UVM ACVP parser |
UVM-formatted vectors are included with evaluation packages. Raw NIST vectors are available from NIST CAVP.
Requesting Access #
To request access to restricted downloads, contact the Dyber IP licensing team:
| Access Level | Requirements | Timeline |
|---|---|---|
| Public | None — available on this documentation site and via public download links | Immediate |
| NDA Required | Mutual NDA executed between Dyber and requesting organization | Typically 1–2 weeks |
| Eval Agreement | Signed evaluation license agreement (NDA included). 90-day term. | Typically 1–2 weeks |
| Dev License | Development license agreement for FPGA synthesis and prototyping | Commercial negotiation |
Contact: ip-sales@dyber.com
Web: dyber.org/contact
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