The Dyber PQC Silicon IP portfolio comprises over 20 licensable IP cores spanning mathematical acceleration, complete algorithm implementations, entropy generation, key management, and protocol offload. All cores are FPGA-validated, architecture-agnostic, and designed for seamless SoC integration via standard AMBA interfaces.
The Number Theoretic Transform is the dominant computational bottleneck for all lattice-based cryptography (ML-KEM and ML-DSA). Dyber offers four NTT configurations spanning three orders of magnitude in area/throughput trade-off.
Core ID
Architecture
Area Class
Throughput Class
Target
DYBER-NTT-R2
Radix-2 butterfly
Ultra-compact
Base
IoT, wearables, constrained devices
DYBER-NTT-R4
Radix-4 butterfly
Compact
Mid-range
Client, mobile, edge computing
DYBER-NTT-R8
Radix-8 butterfly
Standard
High
Server, enterprise, networking
DYBER-NTT-R16
Radix-16 butterfly
Large
Maximum
Datacenter, HPC, high-frequency trading
All NTT engines support configurable moduli (q = 3329 for ML-KEM, q = 8380417 for ML-DSA) and 256/512/1024-point transforms. Detailed specifications available in the NTT Engine Family documentation.
Complete, FPGA-validated implementations of all three NIST post-quantum cryptographic standards. Each accelerator performs full key generation, encapsulation/signing, and decapsulation/verification in hardware.
Core ID
Standard
Security Levels
Operations
DYBER-MLKEM
FIPS 203 (ML-KEM)
512 (L1), 768 (L3), 1024 (L5)
KeyGen, Encapsulate, Decapsulate
DYBER-MLDSA
FIPS 204 (ML-DSA)
44 (L2), 65 (L3), 87 (L5)
KeyGen, Sign, Verify
DYBER-SLH
FIPS 205 (SLH-DSA)
128f, 128s, 256f
KeyGen, Sign, Verify
Performance data demonstrates significant acceleration over software-only implementations, with hardware throughput measured at 12–28× faster than optimized software on modern server-class processors for equivalent operations. Detailed architecture and configuration options are documented in Algorithm Accelerators.
SHA-3/SHAKE is the second most critical building block in PQC after NTT — ML-KEM and ML-DSA use SHAKE extensively for matrix generation, noise sampling, and key derivation. Dyber's hash cores can be licensed standalone or are included as submodules within the algorithm accelerators.
Hardware key lifecycle: generation, secure storage (up to 256 slots), derivation, usage tracking, and guaranteed zeroization. Hardware-enforced isolation between key domains prevents cross-contamination. Formal verification guarantees that key material never appears on external buses.
First-order Boolean and arithmetic masking for all secret-dependent operations. Independently verifiable against TVLA evaluation criteria. Licensed separately.
DYBER-FI-DETECT
Fault Injection Detection
Hardware-based fault detection with redundant computation, temporal redundancy checks, and infection countermeasures. Triggers alert and key zeroization on detected fault.