Release Notes

Version history for the Dyber PQC Silicon IP portfolio. Each release includes updated RTL deliverables, verification suites, documentation, and FPGA validation reports.

v2.0.0 — December 2025 #

CURRENT Major release with architecture-agnostic integration model and expanded algorithm support.

New IP Cores

SLH-DSA Accelerator (DYBER-SLH) — Complete FIPS 205 stateless hash-based signature implementation supporting 128f, 128s, and 256f parameter sets. Provides conservative security assumptions independent of lattice hardness.

Hybrid KEM Bridge (DYBER-HKEM) — Combined classical ECDH + ML-KEM key exchange engine for transitional deployments requiring backward compatibility with existing PKI infrastructure.

TLS Handshake Offload Engine (DYBER-TLS) — End-to-end TLS 1.3 handshake acceleration with integrated ML-KEM key exchange and ML-DSA certificate verification. Offloads the complete cryptographic handshake from the host CPU.

Enhancements

Architecture-Agnostic Bus Interfaces: All cores now ship with unified AMBA AXI4, AXI4-Lite, AXI4-Stream, APB, and AHB interfaces. Same RTL integrates with x86, ARM, RISC-V, or any CPU architecture without modification.

NTT-R16 Engine: New Radix-16 configuration for maximum-throughput datacenter applications. Highest per-core throughput in the portfolio.

Power Analysis Countermeasures: First-order Boolean and arithmetic masking now available as a separately licensed option for all algorithm accelerators. Adds approximately 15–25% area overhead.

Validation

All cores validated on Xilinx UltraScale+ FPGA family with timing closure achieved. Successful portability demonstrated across multiple FPGA generations with different DSP and memory primitive architectures.

v1.2.0 — September 2025 #

New IP Cores

Key Management Unit (DYBER-KMU) — Hardware key lifecycle manager with generation, storage, derivation, usage tracking, and zeroization. Supports up to 256 concurrent key slots with hardware-enforced isolation.

Secure Boot Accelerator (DYBER-SBOOT) — PQC-based secure boot chain verification using ML-DSA signatures. Validates firmware images at hardware speed during boot sequence.

Enhancements

ML-KEM Throughput Improvement: Optimized NTT pipeline scheduling reduces key encapsulation latency by approximately 15% across all security levels.

Extended NIST KAT Coverage: Verification suite now includes complete ACVP test vector support for all algorithm accelerators.

v1.1.0 — June 2025 #

New IP Cores

QRNG Core (DYBER-QRNG) — Quantum random number generator with integrated SP 800-90B health testing and entropy conditioning. Provides hardware-grade entropy for key generation and nonce production.

Enhancements

ML-DSA Signing Optimization: Improved rejection sampling pipeline reduces average signing latency. Deterministic worst-case timing maintained for constant-time guarantees.

Formal Verification Assertions: SVA property libraries now included with all IP cores for integration-level formal verification.

v1.0.0 — March 2025 #

FIRST PRODUCTION RELEASE

IP Cores

NTT Engine Family (DYBER-NTT): Radix-2, Radix-4, and Radix-8 configurations with area/throughput trade-offs spanning IoT to server-class applications.

ML-KEM Accelerator (DYBER-MLKEM): Complete FIPS 203 implementation supporting ML-KEM-512, ML-KEM-768, and ML-KEM-1024 parameter sets.

ML-DSA Accelerator (DYBER-MLDSA): Complete FIPS 204 implementation supporting ML-DSA-44, ML-DSA-65, and ML-DSA-87 parameter sets.

SHA-3/SHAKE Hash Core (DYBER-SHA3): Keccak-f[1600] permutation engine with SHA3-256, SHA3-512, SHAKE-128, and SHAKE-256 modes.

Modular Arithmetic Units (DYBER-ARITH): Barrett reduction, Montgomery multiplication, and polynomial arithmetic building blocks.

Cryptographic Sampling (DYBER-SAMP): Centered binomial distribution and uniform rejection sampling units.

v0.9.0 — December 2024 #

BETA

Pre-production release for evaluation partners. NTT and ML-KEM cores with limited FPGA validation. Provided to select partners under evaluation license for integration feasibility assessment.

Roadmap #