Support & Licensing
Dyber provides dedicated engineering support throughout the integration lifecycle — not just IP deliverables and documentation. Our engagement model ensures successful deployment from initial evaluation through volume production and silicon bring-up.
Engagement Model #
Dyber's IP business is a partnership model, not a download-and-forget transaction. Cryptographic IP integration demands close collaboration on security architecture, verification strategy, certification planning, and platform-specific optimization. Our support infrastructure reflects this reality.
Dedicated integration engineers: Dyber engineers are available for on-site or remote collaboration during integration phases. Our team brings deep expertise in PQC algorithm implementation, FPGA/ASIC integration, side-channel countermeasures, and FIPS certification — the exact skills needed to successfully deploy PQC in production silicon.
Ongoing relationship: Support continues beyond initial integration. As NIST standards evolve, new attack vectors are discovered, or certification requirements change, Dyber provides IP updates and engineering guidance to keep deployed implementations current and secure.
Support Tiers #
| Tier | Scope | Typical Engagement |
|---|---|---|
| Evaluation | Email support, documentation clarification, simulation assistance. Guidance on integration feasibility and resource estimation. | 90-day evaluation period. No-cost access to encrypted RTL and UVM testbench. |
| Development | Dedicated support engineer assigned to the project. Weekly sync calls. Integration guidance including synthesis constraints, timing closure support, driver adaptation, and verification strategy. | Active FPGA development and prototyping. Full source code access. |
| Production | Priority support with defined response time SLAs. On-site availability for critical milestones. ASIC flow collaboration including synthesis, STA, DFT, and gate-level verification. Silicon validation and bring-up support. | Volume production commitment. Full source code including generic RTL for ASIC. |
Specific engineering hours, response time SLAs, and detailed support scope are defined in the commercial agreement and tailored to each engagement.
License Tiers #
| Tier | Delivery Format | Rights & Use Cases |
|---|---|---|
| Evaluation | Encrypted RTL (simulation only) | 90-day assessment. Simulation, verification, and integration feasibility study. No synthesis or physical implementation. |
| Development | Full RTL source code (FPGA-optimized) | Internal development and FPGA prototyping. Synthesis, implementation, and hardware validation. Not for volume production. |
| Production | Full source code + generic RTL | Volume manufacturing rights. ASIC integration with generic (inference-only) RTL. Includes production support and IP updates. |
Delivery & Source Code #
For development and production licenses, Dyber delivers full RTL source code — not obfuscated or encrypted netlists. This enables complete integration flexibility including custom modifications, synthesis optimization for specific process nodes, and full internal audit capability.
| Deliverable | Description | License Level |
|---|---|---|
| Synthesizable RTL | Verilog, SystemVerilog, and VHDL options | Development+ |
| FPGA-Optimized Variant | Xilinx-targeted with DSP inference hints and BRAM optimization | Development+ |
| Generic RTL Variant | Inference-based code with no vendor primitives for ASIC migration | Production only |
| DFT-Ready Structure | RTL structured for scan insertion and BIST integration | Production only |
| UVM Verification Suite | Complete testbench, sequences, reference model, coverage | All tiers |
| Formal Assertions | SVA property libraries for security and protocol verification | All tiers |
| Driver Libraries | Bare-metal C library + reference Linux kernel module | All tiers |
| Documentation | Datasheet, integration guide, register map, security target | All tiers |
Commercial Models #
Dyber offers flexible licensing structures designed to align with diverse business models and volume requirements:
Per-Unit Royalty: Volume-based pricing tied to production units shipped. Low upfront cost with ongoing royalty payments. Best for products with uncertain initial volumes or when minimizing upfront investment is a priority.
Flat License Fee: One-time payment for unlimited deployment within a defined product scope. No per-unit tracking or royalty administration. Best for high-volume products where per-unit cost optimization is critical.
Hybrid Model: Combination of a reduced upfront license fee with lower per-unit royalties. Balances initial investment with volume economics. Best for products with growing but uncertain volume trajectories.
Product Family License: Covers a related product line (e.g., all variants of a server CPU family or a complete DPU product line). Single agreement, simplified administration. Best for platform companies deploying across multiple SKUs.
Enterprise Agreement: Comprehensive multi-IP license covering the complete Dyber portfolio for deployment across multiple product lines. Maximum flexibility with simplified procurement. Best for large organizations with PQC requirements across many products.
Patent Protection #
Dyber's patent portfolio covers novel architectures and implementations in the emerging PQC hardware space. Licensing includes freedom-to-operate under Dyber's patent portfolio for the licensed IP.
Patent coverage: Pending patents cover optimized NTT architectures, integrated side-channel countermeasures, hardware key management techniques, and multi-algorithm acceleration architectures. The patent portfolio provides defensive protection in the rapidly growing PQC market.
Freedom to operate: Licensed partners receive explicit rights under Dyber's patents for all functionality implemented by the licensed IP cores. This eliminates IP risk in the emerging PQC hardware space where patent landscapes are still developing.
Engagement Path #
Dyber recommends a structured engagement that progresses from technical evaluation to production deployment:
| Phase | Activities | Duration |
|---|---|---|
| 1. Technical Deep Dive | Joint technical sessions reviewing specific IP cores aligned with priority products. Architecture presentations with measured performance data. Q&A with Dyber engineering. | 1–2 weeks |
| 2. Evaluation License | 90-day evaluation with simulation rights. Integration feasibility assessment. Benchmark against requirements. Resource estimation for target platform. | 90 days |
| 3. Proof of Concept | Joint development of prototype implementation on FPGA. Real-world integration validation. Performance measurement on hardware. Driver integration and system-level testing. | 2–4 months |
| 4. Commercial Agreement | Development of licensing terms tailored to product roadmap, volume requirements, and strategic objectives. Support scope definition. | Concurrent with Phase 3 |
| 5. Production Integration | Full source code delivery. ASIC integration support (if applicable). Verification collaboration. Certification preparation. Silicon bring-up support. | 3–6 months typical |
Frequently Asked Questions #
Q: Can I evaluate before committing to a license?
Yes. The 90-day evaluation license is free and includes encrypted RTL with full simulation capability plus the complete UVM verification suite. There is no cost and no obligation. The only requirement is a signed evaluation agreement that covers IP confidentiality.
Q: What if I only need signature verification, not signing?
DYBER-MLDSA offers a verify-only configuration that omits the signing pipeline and rejection controller, reducing area by approximately 35–40%. This is ideal for secure boot, certificate validation, and other verification-only applications.
Q: Do I need to license primitives separately if I license an algorithm accelerator?
No. Primitives included as submodules within algorithm accelerators (NTT, SHAKE, modular arithmetic, sampling) are covered by the accelerator license. Separate licensing is only required for standalone primitive instantiation outside of an algorithm accelerator.
Q: How does the IP handle future NIST standard revisions?
Production licenses include IP updates for the duration of the support term. If NIST publishes algorithm corrections or parameter changes, Dyber provides updated RTL and verification suites. The crypto-agile architecture (runtime parameter selection) minimizes the scope of changes required.
Q: Is the IP validated for ASIC, or only FPGA?
Current validation is FPGA-based with production-quality measured results. ASIC integration is supported through joint engineering with the generic RTL variant. Dyber has demonstrated successful portability across multiple FPGA architectures (7-series → UltraScale+), which de-risks the ASIC path. ASIC-specific validation (synthesis, STA, gate-level simulation) is performed collaboratively using the integrator's process technology and design methodology.
Q: Can I get a custom NTT configuration between the standard options?
Yes. Custom configurations are available through engineering engagement. Intermediate parallelism levels, custom moduli, and non-standard transform sizes can be accommodated for specific application requirements.
Q: What is the typical integration timeline?
FPGA integration (connecting to an existing SoC design with AMBA bus infrastructure) typically completes in 3–6 months from development license to validated hardware. This compares to 18–24 months for ground-up PQC implementation. ASIC integration timeline depends on the integrator's design cycle and process node selection.
Contact #
Dyber, Inc. — PQC Silicon IP
IP Licensing & Evaluation: ip-sales@dyber.com
Technical Questions: ip-support@dyber.com
General Inquiries: info@dyber.com
Web: dyber.org/contact
Executive Contact: Zachary Kleckner, Founder & CEO — info@dyber.org
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