QCORE-C1 Integration Guide
OEM integration handbook covering QLI interface bring-up, power delivery requirements, multi-chiplet topology design, and packaging options for 2.5D, 3D, and MCM configurations. This document is intended for SoC architects and integration engineers embedding the QCORE-C1 into host systems.
Packaging Options #
The QCORE-C1 is delivered as a Known-Good-Die (KGD) for integration into multi-chip packages. Three primary packaging configurations are supported:
| Configuration | Description | QLI Bandwidth | Best For |
|---|---|---|---|
| 2.5D Interposer | Silicon interposer with through-silicon vias (TSVs). QCORE-C1 mounted alongside host die on shared interposer. | Up to 25.6 GB/s | High-performance SoCs, datacenter processors |
| 3D Stacked | QCORE-C1 stacked directly on host die using micro-bumps. Shortest QLI trace length. | Up to 25.6 GB/s | Space-constrained designs, mobile/edge |
| MCM (Multi-Chip Module) | Side-by-side on organic substrate with flip-chip or wire-bond. Simplest assembly. | Up to 12.8 GB/s | Cost-sensitive, rapid prototyping, legacy |
Die Specifications #
| Parameter | SKY130 Prototype | GF22FDX Production |
|---|---|---|
| Die dimensions | 2.0 mm × 2.0 mm | 1.2 mm × 1.2 mm (projected) |
| Die area | 4.0 mm² | 1.44 mm² (projected) |
| Bump pitch (flip-chip) | 150 μm | 100 μm |
| Wire-bond pad pitch | 80 μm | 60 μm |
| I/O pad count | 286 total | 286 total |
| QLI signal pads | 128 TX + 128 RX + 30 control | Same |
| Die thickness | 725 μm (standard) | 100 μm (thinned for 3D) |
QLI Interface Bring-Up #
The QLI interface initialization follows a deterministic sequence managed by hardware state machines. The host is responsible for providing the reference clock, releasing reset, and exchanging initial credits.
Initialization Sequence
| Phase | Duration | Host Action | QCORE-C1 Response |
|---|---|---|---|
| 1. Power-on | — | Apply VDD_CORE (0.8V) and VDD_IO (1.8V/3.3V) | Internal POR sequence |
| 2. Clock stable | <1 ms | Provide stable reference clock to CLK_REF | PLL locks, generates internal clocks |
| 3. Reset release | 10 μs | Deassert RESET_N (active-low) | Begins QLI PHY calibration |
| 4. Link training | <100 μs | Monitor INIT_DONE signal | TX/RX alignment, skew calibration |
| 5. Credit exchange | <10 μs | Send 32 initial TX credits | Returns 32 initial RX credits |
| 6. Link active | — | LINK_UP asserted — ready for operations | Begins accepting crypto commands |
Power Delivery #
| Rail | Voltage | Tolerance | Current (Typ) | Current (Max) | Description |
|---|---|---|---|---|---|
| VDD_CORE | 0.80 V | ±5% | 180 mA | 250 mA | Core digital logic |
| VDD_SRAM | 0.80 V | ±5% | 40 mA | 60 mA | 64KB secure SRAM |
| VDD_IO | 1.80 V | ±10% | 120 mA | 200 mA | QLI I/O drivers |
| VDD_PLL | 0.80 V | ±3% | 15 mA | 25 mA | PLL analog supply |
Decoupling Requirements
Each power rail requires local decoupling capacitance placed within 1mm of the die power bumps. Recommended decoupling: 10× 100nF MLCC (0201) per rail plus 2× 10μF bulk capacitor per rail. The VDD_PLL rail requires additional filtering — a ferrite bead (600Ω @ 100MHz) in series with the supply is recommended to isolate analog noise from digital switching.
Thermal Considerations #
| Parameter | SKY130 | GF22FDX (Projected) |
|---|---|---|
| Typical power dissipation | 350 mW | 200 mW |
| Maximum power dissipation | 500 mW | 350 mW |
| Junction temperature (max) | 125°C | 125°C |
| θJA (flip-chip on interposer) | 25 °C/W | 30 °C/W |
| θJA (wire-bond MCM) | 35 °C/W | 40 °C/W |
At 500mW maximum power dissipation and 35°C/W thermal resistance (worst-case MCM), the QCORE-C1 junction temperature reaches approximately 17.5°C above ambient. No dedicated heatsink is required in most integration scenarios — the host SoC's thermal solution provides adequate heat dissipation through the shared substrate.
Signal Integrity Guidelines #
QLI signal integrity is critical for reliable high-speed operation. Follow these design rules for the interconnect between the QCORE-C1 and host QLI bridge:
| Parameter | Requirement |
|---|---|
| Trace impedance | 50Ω single-ended (±10%) |
| Maximum trace length (2.5D) | 10 mm |
| Maximum trace length (MCM) | 25 mm |
| Trace length matching (within group) | ±0.5 mm |
| TX-to-RX isolation | Minimum 3× trace width spacing or ground guard |
| Reference plane | Continuous ground plane immediately below signal layer |
| Via transitions | Maximum 2 per signal (with ground stitching vias) |
Design Review Service #
Dyber offers a complimentary design review for OEM customers integrating the QCORE-C1. The review covers SoC floorplan assessment, QLI PHY layout verification, power delivery network analysis, and thermal simulation review. Contact chiplets@dyber.org to schedule your design review.