🠛 QCORE-C1 › QLI Protocol Specification
QLI Protocol Specification
DYBER-QLI-ARCH-001
Rev 0.1 — December 2025
Complete QLI v0.1 protocol reference: 128-bit parallel DDR PHY, packet format, credit-based flow control, CRC-32/KMAC-128 integrity, and QLI-SHORT/STANDARD/EXTENDED configurations. This page provides the formal protocol specification; for integration guidance see the QLI Interface Reference .
Protocol Overview #
QLI Protocol Stack
Layer Function Key Parameters
Transaction Layer Command dispatch, completion, register access 10 opcodes, 16-bit tags Data Link Layer Credit flow control, CRC-32, optional KMAC-128 32 initial credits, 8-bit counters Physical Layer 128-bit DDR parallel signaling, clock forwarding 1.8V I/O, 50Ω impedance
Physical Layer Specification #
Parameter Value
Data width 128 bits TX + 128 bits RX (full-duplex) Signaling Single-ended CMOS, DDR (data valid on both clock edges) Clock forwarding Source-synchronous, 1 TX_CLK + 1 RX_CLK Per-clock bandwidth 256 bits/edge × 2 edges = 512 bits/cycle Bandwidth @ 100 MHz 6.4 GB/s per direction, 12.8 GB/s aggregate Bandwidth @ 200 MHz (GF22FDX) 12.8 GB/s per direction, 25.6 GB/s aggregate Lane grouping 4 × 32-bit lanes with per-lane valid signals Voltage levels 1.8V CMOS (VDD_IO)
QLI Packet Structure (64-byte aligned):
┌──────────┬──────────────────────────┬────────────┬──────────────â”
│ Header │ Payload │ CRC-32 │ KMAC-128 │
│ (8 bytes)│ (variable: 0–4068 bytes) │ (4 bytes) │ (16 bytes, │
│ │ │ mandatory │ optional) │
└──────────┴──────────────────────────┴────────────┴──────────────┘
Header (8 bytes):
┌─────────┬─────────┬──────────┬─────────┬───────────â”
│ OPCODE │ FLAGS │ LENGTH │ TAG │ RESERVED │
│ [7:0] │ [15:8] │ [31:16] │ [47:32] │ [63:48] │
│ 8 bits │ 8 bits │ 16 bits │ 16 bits │ 16 bits │
└─────────┴─────────┴──────────┴─────────┴───────────┘
Packet Configurations
Type Total Header Payload CRC MAC Use Case
QLI-SHORT 64 B 8 B 52 B 4 B — Register access, commands QLI-STANDARD 256 B 8 B 244 B 4 B — Single polynomial transfer QLI-EXTENDED 4096 B 8 B 4068 B 4 B 16 B Bulk key/ciphertext transfer
Opcode Definitions #
Opcode Name Dir Packet Type Description
0x01WRITE_REG H→Q SHORT Write 32-bit value to MMIO register 0x02READ_REG H→Q SHORT Request register read 0x03READ_RSP Q→H SHORT Register read response with data 0x10DATA_WRITE H→Q STD/EXT Bulk write to SRAM (public key, seed) 0x11DATA_READ H→Q SHORT Request bulk SRAM read 0x12DATA_RSP Q→H STD/EXT Bulk read response with data 0x20CMD_DISPATCH H→Q SHORT Submit ML-KEM operation 0x21CMD_COMPLETE Q→H SHORT Operation completion notification 0x30CREDIT_UPDATE Both SHORT Credit return (piggyback or dedicated) 0xF0LINK_MGMT Both SHORT Training, power state transitions
Credit-Based Flow Control #
Credit Flow Control Protocol:
Host QCORE-C1
│ │
│──── LINK_MGMT(credits=32) ───────────→│ Initial credit exchange
│â†â”€â”€â”€ LINK_MGMT(credits=32) ────────────│ at link-up
│ │
│──── DATA_WRITE (credit−1) ───────────→│ Each TX consumes 1 credit
│──── DATA_WRITE (credit−1) ───────────→│
│ │
│â†â”€â”€â”€ CREDIT_UPDATE(+2) ────────────────│ Receiver returns credits
│ │ as buffers are freed
│──── CMD_DISPATCH (credit−1) ─────────→│
│ │
│â†â”€â”€â”€ CMD_COMPLETE ─────────────────────│ Completions are
│â†â”€â”€â”€ CREDIT_UPDATE(+1) ────────────────│ credit-free (reserved pool)
Parameter Value Notes
Initial credits 32 Exchanged during CONFIG phase of link training Max credits 255 8-bit counter per direction Credit granularity 1 packet Regardless of packet size (SHORT/STD/EXT) Stall behavior TX blocked Transmitter pauses until credit received Credit timeout 1 ms Link error if no credits returned within timeout
Integrity Verification #
CRC-32 (mandatory, all packets): Polynomial 0x04C11DB7 (IEEE 802.3). Computed over header + payload bytes. Appended as 4-byte little-endian trailer. Detects all burst errors ≤32 bits.
KMAC-128 (optional, QLI-EXTENDED): NIST SP 800-185 KMAC with customization string "QLI-v0.1". 128-bit MAC appended after CRC-32. Per-session key derived during link training via Keccak-based key agreement. Required for all transfers containing secret key material.
Link Training FSM #
State Code Timeout Next State Action
RESET 0x00 — DETECT POR complete, release RESET_N DETECT 0x01 1 μs POLLING Detect partner presence via TX/RX activity POLLING 0x02 10 μs TRAINING Lock PLL to received clock, verify frequency TRAINING 0x03 50 μs CONFIG Send/receive PRBS-7 pattern, measure BER CONFIG 0x04 10 μs ACTIVE Exchange credits, negotiate packet sizes ACTIVE 0x05 — — Normal operation, LINK_UP asserted