QLI vs UCIe Comparison
Technical comparison of Dyber's Quantum Lattice Interface (QLI) against the Universal Chiplet Interconnect Express (UCIe) standard: latency, signaling approach, design complexity, licensing terms, and suitability for cryptographic workloads.
Architecture Comparison #
| Feature | QLI v0.1 | UCIe 1.0/1.1 |
|---|---|---|
| Designed for | Cryptographic chiplets (PQC-optimized) | General-purpose chiplet interconnect |
| Signaling | 128-bit parallel DDR (single-ended CMOS) | SERDES-based (16/32/64 lanes) |
| Clock | Source-synchronous forwarded clock | Embedded clock (CDR recovery) |
| Voltage | 1.8V CMOS | 0.8–0.9V (advanced node) or 1.2V |
| Protocol layers | 3 (PHY, Data Link, Transaction) | 4 (PHY, Die-to-Die Adapter, Protocol, Application) |
| Packet sizes | 64 / 256 / 4096 bytes | Variable (flit-based, 256-bit) |
| Standardization | Dyber proprietary, royalty-free | UCIe Consortium (membership required) |
Performance Comparison #
| Metric | QLI v0.1 | UCIe 1.0 | Analysis |
|---|---|---|---|
| Latency (2.5D) | <3 ns | <5 ns | QLI's parallel bus avoids SERDES serialization delay |
| Latency (MCM) | <5 ns | <10 ns | No CDR lock-in overhead |
| Bandwidth (per direction) | 6.4–12.8 GB/s | 4–32 GB/s | UCIe scales wider but QLI sufficient for crypto |
| Link training time | <100 μs | <1 ms | Simpler PHY = faster training |
| Credit-to-credit turnaround | 1 cycle | 4–8 cycles | Dedicated credit bus vs in-band |
| Bandwidth efficiency | 92–98% | 85–95% | Lower protocol overhead |
Design Complexity #
| Aspect | QLI | UCIe |
|---|---|---|
| RTL design effort | 6–9 months | 12–18 months |
| PHY complexity | Simple CMOS drivers (no SERDES, no CDR) | High-speed SERDES + CDR + equalization |
| Process node dependency | Works on 130nm+ (proven on SKY130) | Optimized for 5nm–16nm (SERDES IP) |
| Analog IP required | PLL only | PLL + SERDES + CDR + DFE |
| Verification effort | ~50K test vectors | ~200K+ test vectors |
| Area overhead (130nm) | 0.2 mm² | ~1.5 mm² (estimated with SERDES) |
Licensing & Business Terms #
| Term | QLI | UCIe |
|---|---|---|
| License fee | None (royalty-free) | UCIe Consortium membership + IP licensing |
| Per-unit royalty | None | Depends on IP provider (typically $0.05–0.50/die) |
| Specification access | Free (published by Dyber) | Consortium members only |
| IP availability | Synthesizable RTL from Dyber | Licensed IP from Synopsys, Cadence, Alphawave |
| Modification rights | Full customization permitted | Must maintain compliance for interop |
| Ecosystem support | Dyber chiplets only (currently) | Multi-vendor ecosystem (Intel, AMD, ARM, etc.) |
Security Features #
| Feature | QLI | UCIe |
|---|---|---|
| Link integrity | CRC-32 (mandatory on all packets) | CRC (optional, configurable) |
| Authentication | KMAC-128 MAC (built-in, per-session key) | IDE (optional, AES-GCM-256) |
| Key agreement | Keccak-based (leverages on-die Keccak core) | Separate key management required |
| Crypto-specific optimizations | Packet sizes matched to polynomial/key sizes | Generic flit structure |
| Side-channel isolation | Constant-time credit returns, no data-dependent timing | Not specified |
When to Use Each #
| Scenario | Recommendation | Rationale |
|---|---|---|
| PQC accelerator chiplet (Dyber products) | QLI | Purpose-built, lowest latency, zero licensing cost |
| Multi-vendor chiplet ecosystem | UCIe | Industry standard interoperability |
| Older process nodes (65nm–180nm) | QLI | No SERDES required, works on any node |
| Advanced packaging with HBM | Either (UCIe has ecosystem advantage) | Both support 2.5D interposer |
| Cost-sensitive designs | QLI | No license fees, simpler PHY, less silicon area |
| Maximum bandwidth (>25 GB/s) | UCIe | SERDES scales to higher data rates |
| Security-critical applications | QLI | Built-in KMAC-128 authentication, crypto-optimized |
See also: QLI Protocol Specification for complete protocol details, Integration Guide for OEM implementation guidance.