QCORE-C1 Release Notes
This document tracks RTL revisions, tapeout milestones, silicon errata, and design rule updates for the QCORE-C1 post-quantum cryptographic accelerator chiplet. The QCORE-C1 is currently in pre-silicon development targeting SkyWater SKY130 prototype fabrication.
Current Release: RTL v0.9.5 #
RTL v0.9.5 represents the feature-complete milestone for the QCORE-C1 chiplet. All major functional blocks — the 8-way Radix-16 NTT array, Keccak-f[1600] hashing core, polynomial arithmetic unit, CBD sampler, Kyber control FSM, and QLI interface — have achieved RTL completion and are undergoing verification closure.
Key Achievements
| Metric | Target | Achieved | Status |
|---|---|---|---|
| RTL Completion | 100% | 95% | On track |
| Functional Verification | 100% | 87% | In progress |
| Code Coverage | >95% | 91% | In progress |
| Lint Warnings | 0 critical | 0 critical | ✓ Complete |
| Synthesis (SKY130) | Clean | Clean | ✓ Complete |
| STA Timing Closure | Met | Met @ 100MHz | ✓ Complete |
New in v0.9.5 #
NTT Array Optimization
The 8-way Radix-16 NTT butterfly array now achieves full pipeline utilization with zero-bubble scheduling. Twiddle factor ROM has been compressed by 40% using symmetry exploitation, reducing die area by approximately 0.05 mm² without impacting throughput. The NTT forward and inverse transforms complete a 256-coefficient polynomial in 16 clock cycles.
QLI Protocol Controller v0.1
Initial implementation of the Quantum Lattice Interface protocol layer with credit-based flow control, CRC-32 packet integrity, and optional KMAC-128 authentication. The link training FSM has been validated in FPGA co-simulation against a QLI host bridge model.
Keccak-f[1600] Unrolled Pipeline
The Keccak core has been re-architected from a 24-round iterative design to a 6-stage unrolled pipeline (4 rounds per stage), reducing hash latency from 24 cycles to 6 cycles. SHA-3/SHAKE-128/SHAKE-256 modes are supported with automatic padding.
Power Management Integration
Added clock gating for idle NTT lanes, Keccak core auto-shutdown, and QLI low-power link states (L1/L2). Estimated power reduction of 35% during idle periods on the SKY130 prototype.
Resolved Issues #
| Issue ID | Module | Description |
|---|---|---|
| QC1-142 | NTT Array | Fixed coefficient reduction modulo q=3329 overflow on back-to-back inverse NTT operations |
| QC1-138 | Keccak Core | Corrected SHA-3 padding for messages with length exactly divisible by rate parameter |
| QC1-131 | QLI PHY | Resolved DDR sampling metastability on RX path at clock domain boundary |
| QC1-127 | CBD Sampler | Fixed binomial distribution bias for η=3 (ML-KEM-1024) noise generation |
| QC1-119 | Kyber FSM | Corrected encapsulation state machine hang when decapsulation fails integrity check |
| QC1-115 | SRAM Controller | Fixed arbitration deadlock between NTT and Keccak concurrent SRAM access |
Known Issues #
| Issue ID | Module | Description | Workaround |
|---|---|---|---|
| QC1-148 | QLI Training | Link training timeout occurs if host delays credit initialization by >100μs | Ensure host sends initial credits within 50μs of INIT_DONE |
| QC1-145 | DFT | Scan chain 3 (Keccak) has insufficient coverage in ATPG patterns | None; additional patterns being generated |
| QC1-143 | Clock Gating | NTT lane wake-up adds 2 extra cycles vs. spec (4 cycles instead of 2) | Pre-wake NTT lanes before submitting operations |
Tapeout Status #
The QCORE-C1 prototype is targeting the SkyWater SKY130 process via the Efabless chipIgnite shuttle program. Current tapeout preparation status:
| Milestone | Status | Target Date |
|---|---|---|
| RTL freeze | In progress | January 2026 |
| Verification closure (>95% coverage) | In progress | January 2026 |
| Synthesis + floorplan (OpenLane 2) | Complete | — |
| STA sign-off @ 100MHz | Complete | — |
| DRC clean (SKY130) | In progress | February 2026 |
| LVS clean | In progress | February 2026 |
| GDS-II submission (chipIgnite) | Pending | Q1 2026 |
Previous Releases #
RTL v0.9.0 — November 2025
First feature-complete candidate. All major blocks integrated at top level. QLI PHY operational in loopback mode. NTT array validated against reference ML-KEM test vectors (NIST ACVP). Initial OpenLane 2 synthesis achieved timing closure at 80MHz.
RTL v0.8.0 — September 2025
NTT array and Keccak core integrated. Kyber FSM supporting ML-KEM-768 KeyGen and Encaps. SRAM controller with dual-port arbitration. FPGA prototype on XCZU7EV demonstrating end-to-end ML-KEM operations.
RTL v0.5.0 — June 2025
Individual block-level verification complete. NTT butterfly unit, Keccak-f[1600] permutation, polynomial arithmetic unit, and CBD sampler validated independently. Initial QLI PHY RTL with TX/RX datapaths.
Development Roadmap #
| Version | Target | Key Features |
|---|---|---|
| v0.9.6 | February 2026 | RTL freeze, DRC/LVS clean, final verification closure |
| v1.0.0 | Q1 2026 | Tapeout candidate — GDS-II submission to chipIgnite |
| v1.1.0 (GF22FDX) | Q3 2026 | Production port to GlobalFoundries 22FDX, target 500MHz+ |