Secure AXI Fabric (tamper interlocks, per-master access control, crypto MMU), QLI Die-to-Die PHY (radix-16 native), PCIe Gen4 x4 Controller, and AXI-Lite CSR integration harness. All items are on the development roadmap.
Development roadmap. All IP cores in the Secure Interconnect & Integration family are currently on the development roadmap. None are available for licensing today. Contact us to discuss your integration requirements and timeline.
The following cores are planned for the Secure Interconnect & Integration family. Each addresses a critical integration requirement for post-quantum SoC designs.
Full-crossbar AXI4 interconnect with tamper interlocks, per-master access control policies, and an integrated crypto MMU for address-space isolation. Designed for multi-master SoC topologies where each bus master requires distinct security privileges.
Physical layer for Quantum Lattice Interconnect (QLI) die-to-die communication with native radix-16 signaling. Enables high-bandwidth, low-latency chiplet-to-chiplet links for multi-die PQC accelerator packages.
PCIe Generation 4 endpoint controller with four lanes. Provides the host interface for pluggable PQC accelerator cards and co-processors. Includes DMA engine, MSI-X interrupt support, and configuration space management.
Standardized AXI-Lite control and status register (CSR) harness for integrating Dyber IP cores into SoC designs. Provides a uniform register interface, interrupt aggregation, and a consistent software abstraction layer across all cores.
Post-quantum cryptographic accelerators are only as secure as the bus fabric, host interfaces, and integration infrastructure that connect them. A compromised interconnect undermines every algorithm running on it. The Secure Interconnect & Integration family closes that gap.
The Secure AXI Fabric enforces fine-grained access policies at the interconnect level. Each bus master receives only the address-space visibility its security context permits. Combined with tamper interlocks, the fabric detects and contains unauthorized access attempts before they reach any peripheral.
The QLI PHY uses radix-16 signaling natively, enabling higher symbol rates per pin compared to binary or PAM-4 alternatives. Designed for the tight latency and bandwidth requirements of multi-die cryptographic accelerator packages.
Contact us to discuss your integration requirements, target timeline, and how these planned IP cores fit into your SoC architecture.