Boolean and arithmetic masking wrappers, shuffled sampling, power-flattening controller (FD-SOI body-bias native), and fault-injection sensors. All items are on the development roadmap.
Side-channel attacks and fault injection bypass algorithmic security entirely. Correct cryptographic implementations can leak secrets through power consumption, electromagnetic emanations, and timing variation. Physical fault injection can force incorrect outputs that reveal key material through differential analysis.
Dyber is developing a family of protection IP that wraps existing PQC and symmetric cores with countermeasures against these physical attacks. All items below are on the development roadmap. Contact us to discuss your requirements and timeline.
Roadmap notice. All cores on this page are in active development. None are available for licensing today. Product specifications, interfaces, and timelines are subject to change. Contact Dyber to discuss your requirements and to receive updates as cores reach availability.
First-order Boolean masking for PQC and symmetric cores. Splits sensitive intermediate values into randomized shares, ensuring that no single wire carries exploitable information. Targets constant-time execution across all data-dependent operations.
Arithmetic masking for lattice-based operations where Boolean masking is not directly applicable. Converts between Boolean and arithmetic domains without unmasking. Designed for integration with ML-KEM and ML-DSA polynomial arithmetic paths.
Randomized execution ordering for coefficient sampling and polynomial operations. Prevents an attacker from correlating power traces to specific coefficient positions. Configurable shuffle depth for area and latency trade-offs.
Active power consumption equalization using FD-SOI body-bias control. Dynamically adjusts transistor threshold voltages to flatten the power signature during cryptographic operations. Native FD-SOI integration, no external regulators required.
Voltage glitch detectors, clock frequency monitors, and laser fault-injection sensors. Detects physical tampering attempts and triggers configurable responses: computation abort, key zeroization, or tamper flag assertion.
A cryptographic core can produce byte-exact outputs against every NIST test vector and still leak its private key through a side channel. Power analysis, electromagnetic probing, and fault injection operate below the abstraction layer of algorithmic correctness. Protection must be designed into the hardware from the start.
Differential and correlation power analysis extract key bits by measuring supply current during cryptographic operations. Masking and power flattening are the primary countermeasures.
Near-field EM probes can localize leakage to individual logic gates. Spatial diversity and noise injection complement masking to close this channel.
Voltage glitches, clock manipulation, and focused laser pulses can induce computation errors. Differential fault analysis of incorrect outputs reveals key material.
Side-channel protection wraps and hardens the algorithm cores in these families.
ML-KEM, ML-DSA, and SLH-DSA. The primary targets for masking and shuffled sampling countermeasures.
AES, SHA-2, HMAC, HKDF. Boolean masking wrappers apply directly to these cores.
The secure execution environment where fault-injection sensors and tamper response logic integrate.
All side-channel and fault protection IP is on the development roadmap. Contact us to discuss your threat model, target process node, and timeline.