AES-256 Engine | Dyber IP Cores

Overview

A complete AES-256 encryption and decryption engine. Iterative architecture processes one round per clock cycle (14 cycles for AES-256). Uses a packed-constant S-box implementation. Foundation block for the GCM, XTS, and CTR mode cores.

Key Features

FIPS 197 AES-256 encrypt and decrypt
Iterative: 14 rounds, 1 per cycle
Packed-constant S-box
Foundation for GCM/XTS/CTR mode cores

Benefits

Silicon-efficient single-block engine
Shared across all AES mode variants
Well-characterized area and timing

Standards & Verification

Standards compliance: NIST FIPS 197

Verification: Verified vs FIPS 197 Appendix C.3 Known Answer Test.

"Verified" means RTL byte-exact against official test vectors. It does not imply FIPS 140-3 certification or foundry sign-off.

Availability & Deliverables

Available Verified soft IP, foundry-portable RTL.

Standard Deliverables

Synthesizable SystemVerilog RTL
Self-checking testbench(es)
Python golden reference model
cocotb regression
Synthesis scripts
Integration/user guide

Firm/hard IP (hardened netlist for a target node) available on foundry enablement.

AES-256 Engine.